The semiconductor industry is entering a new phase of packaging density with the development of electronic modules containing multiple integrated circuit (IC) die. Recent increases in semiconductor device clock speeds, the number of inputs and outputs, die densities, and pad densities have made it desirable to package a variety of different integrated circuits, such as microprocessors, ASIC devices, and memory devices, together into multi-chip modules (MCM) and hybrids to create high performance products.
A factor identified by the industry as critical to the successful development of multi-chip modules is the availability of "known good die" (KGD). A known good die is a die in which there is a very high confidence level that it will operate reliably over its intended lifetime. With many die mounted into a multi-chip module, the compound effect of the individual yields of the different die becomes an issue. For example, twenty die assembled into a multi-chip module (MCM) having individual yields of 95% will produce an MCM first pass test yield of only 35%. Such a low yield will result in an undesirable quantity of material scrap and require very expensive and labor intensive rework. The use of known good die is required to achieve optimal first pass test yields in producing multi-chip modules in either a chips first or chips last assembly approach.
Since semiconductor die exhibit early life failures when tested across time, "burn-in" testing at elevated temperatures is used to identify potentially defective die and separate them from the remaining known good die. The potentially defective die are discarded and only the remaining known good die are placed in their final packaging configuration. One current test method uses mechanical probe needles at wafer level probe. A drawback to this method is that the mechanical probe needles have limited density capability and leave considerable damage in the form of impressions on the bond pad. These impressions are unacceptable in the chips "first" MCM assembly approach. Another current test method uses TAB (tape automated bonding) tape at die level test. A drawback to this method is that TAB tape in higher density configurations is costly and requires circuit area for application to a packaging scheme. In addition, the availability of TAB tape is limited at present.
Currently, the most widely used method in obtaining known good die (KGD) is packaging the die, testing the die in the package, and removing the die from the package. The extra material and processing required by this method make this form of testing very expensive. In addition, this temporary packaging method reduces integrated circuit density since it requires the die to have extra or enlarged pads for wire bonding to connect the signal leads of the package. This method of testing also has an adverse affect on die reliability due to the fact that after removing the die from the test package, the bond wires are broken off before the die is assembled into the final package configuration. Removal of the bond wires tends to damage the bond pads on the device, resulting in lower yielding bonds.
In light of present test methods, manufacturers must currently decide between assembling multi-chip modules or hybrids with pre-tested, but damaged semiconductor die or die which have not been tested or conditioned.
Accordingly, a need exists for an interconnect system that can be used to test semiconductor die or wafers without damaging them.